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| P4C164L LOW POWER 8K x 8 STATIC CMOS RAM FEATURES VCC Current (Commercial/Industrial) -- Operating: 55 mA -- CMOS Standby: 3 A Access Times --80/100 (Commercial or Industrial) Single 5 Volts 10% Power Supply Easy Memory Expansion Using CE1, CE2 and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages --28-Pin 300 and 600 mil DIP --28-Pin 330 mil SOP DESCRIPTION The P4C164L is a 64K density low power CMOS static RAM organized as 8Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V10% tolerance power supply. Access times of 80 ns and 100 ns are available. CMOS is utilized to reduce power consumption to a low level. The P4C164L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A12. Reading is accomplished by device selection (CE1 low CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE1 or OE is HIGH or WE or CE2 is LOW. Package options for the P4C164L include 28-pin 300 and 600 mil DIP and 28-pin 330 mil SOP packages. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DIP (P5, P6), SOP (S5) TOP VIEW Document # SRAM116 REV B Revised June 2007 1 P4C164L RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Commercial (0C to 70C) Industrial (-40C to 85C) Supply Voltage 4.5V VCC 5.5V 4.5 VCC 5.5V MAXIMUM RATINGS(1) Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol V CC VTERM TA STG IOUT ILAT Parameter Supply Voltage with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Ambient Temperature Storage Temperature Output Current into Low Outputs Latch-up Current >200 Min -0.5 -0.5 -55 -65 Max 7.0 VCC + 0.5 125 150 25 Unit V V C C mA mA DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Symbol VOH VOL VIH VIL ILI ILO ISB Parameter Output High Voltage (I/O0 - I/O7) Output Low Voltage (I/O0 - I/O7) Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC Current TTL Standby Current (TTL Input Levels) VCC Current CMOS Standby Current (CMOS Input Levels) GND VIN VCC GND VOUT VCC CE VIH Ind./Com. Ind./Com. Test Conditions IOH = -1mA, VCC = 4.5V IOL = 2.1mA 2.2 -0.5 -2 -2 (3) Min 2.4 Max Unit V 0.4 VCC + 0.3 0.8 +2 +2 V V V A A VCC = 5.5V, IOUT = 0 mA CE1 = VIH or CE2 = VIL VCC = 5.5V, IOUT = 0 mA CE1 VCC -0.2V or CE2 0.2V 100 A ISB1 3 A Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Document # SRAM116 REV B Page 2 of 11 P4C164L CAPACITANCES(4) (VCC = 5.0V, TA = 25C, F = 1.0 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Max 7 9 Unit pF pF POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current Temperature Range Ind. & Comm. * -80 55 -100 55 Unit mA *Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e. CE and WE VIL (max), OE is high. Switching inputs are 0V and 3V. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) -80 Min 80 80 80 10 10 30 10 10 30 Max Min 100 100 100 -100 Max Symbol t RC tAA t AC tOH tLZ t HZ tOE tOLZ t OHZ t PU t PD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time Unit ns ns ns ns ns ns 40 5 20 0 80 0 5 40 ns ns 20 ns ns 100 ns Document # SRAM116 REV B Page 3 of 11 P4C164L READ CYCLE NO. 1 (OE CONTROLLED)(1) OE READ CYCLE NO. 2 (ADDRESS CONTROLLED) CE READ CYCLE NO. 3 (CE1,CE2 CONTROLLED) NOTES: Notes: 5. WE is HIGH for READ cycle. 6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW and CE2 transition HIGH. 8. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. READ Cycle Time is measured from the last valid address to the first transitioning address. 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them. Document # SRAM116 REV B Page 4 of 11 P4C164L AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) -80 Symbol Parameter Min Max tWC tCW tAW tAS tWP tAH tDW t DH tWZ tOW Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 10 80 70 70 0 60 0 40 0 30 10 -100 Min 100 80 80 0 60 0 40 0 30 Max Unit ns ns ns ns ns ns ns ns ns ns WE WRITE CYCLE NO. 1 (WE CONTROLLED)(6) Notes: 11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show tWZ and tOW. 13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a high impedance state. 14. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM116 REV B Page 5 of 11 P4C164L TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6) CE AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 TRUTH TABLE Mode Standby Standby DOUT Disabled Read Write CE 1 H X L L L CE2 X L H H H OE X X H L X WE X X H H L I/O High Z High Z High Z DOUT High Z Power Standby Standby Active Active Active Figure 1. Output Load * including scope and test fixture. Figure 2. Thevenin Equivalent Note: Because of the high speed of the P4C164L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.77V (Thevenin Voltage) at the comparator input, and a 589 resistor must be used in series with DOUT to match 639 (Thevenin Resistance). Document # SRAM116 REV B Page 6 of 11 P4C164L DATA RETENTION CHARACTERISTICS Symbol V DR ICCDR t CDR tR Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Condition Min 2.0 Typ.* VCC = 2.0V 3.0V 1 1 Max VCC = 2.0V 3.0V 3 3 Unit V A ns ns CE1 VCC - 0.2V or CE2 0.2V, VIN VCC - 0.2V or VIN 0.2V tRC 0 *TA = +25C tRC = Read Cycle Time This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM116 REV B Page 7 of 11 P4C164L ORDERING INFORMATION SELECTION GUIDE The P4C164L is available in the following temperature, speed and package options. Temperature Range Commercial Speed (ns) Package Plastic DIP (300 mil) Plastic DIP (600 mil) Plastic SOP (450 mil) Industrial Plastic DIP (300 mil) Plastic DIP (600 mil) Plastic SOP (450 mil) 80 -80P3C -80P6C -80SC -80P3I -80P6I -80SI 100 -100P3C -100P6C -100SC -100P3I -100P6I -100SI Document # SRAM116 REV B Page 8 of 11 P4C164L Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P5 28 (300 mil) Min Max 0.210 0.014 0.023 0.045 0.070 0.008 0.014 1.345 1.400 0.270 0.300 0.300 0.380 0.100 BSC 0.430 0.115 0.150 0 15 PLASTIC DUAL IN-LINE PACKAGE (300 mil) Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P6 28 (600 mil) Min Max 0.090 0.200 0.000 0.070 0.014 0.020 0.015 0.065 0.008 0.012 1.380 1.480 0.485 0.550 0.600 0.625 0.100 BSC 0.600 TYP 0.100 0.200 0 15 PLASTIC DUAL IN-LINE PACKAGE (600 mil) Document # SRAM116 REV B Page 9 of 11 P4C164L Pkg # # Pins Symbol A A1 B C D e E H L S5 28 (330 mil) Min Max 0.079 0.102 0.000 0.008 0.012 0.020 0.004 0.008 0.701 0.717 0.050 BSC 0.331 0.346 0.457 0.488 0.016 0.050 0 8 SOIC/SOP SMALL OUTLINE IC PACKAGE (S) Document # SRAM116 REV B Page 10 of 11 P4C164L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A B ISSUE DATE Oct-05 Aug-06 Jun-07 SRAM116 P4C164L LOW POWER 8K x 8 STATIC CMOS RAM ORIG. OF CHANGE JDB JDB JDB DESCRIPTION OF CHANGE New Data Sheet Added Lead Free Designation Corrected SOP package details Document # SRAM116 REV B Page 11 of 11 |
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